EPROMs, or electrically-programmable ROMs, are field-effect devices with a floating-gate structure. An EPROM floating gate is programmed by applying proper voltages to the source, drain and control gate of each cell, causing high current through the source-drain path and the charging of the floating gate by hot electrons. The EPROM device is erased by ultraviolet light, which requires a device package having a quartz window above the semiconductor chip. Packages of this type are expensive in comparison with the plastic packages ordinarily used for other memory devices such as DRAMs (dynamic random-access memories). For this reason, EPROMs are generally more expensive than plastic-packaged devices. EPROM devices of this type, and methods of manufacture, are disclosed in U.S. Patent Nos. 3,984,822, 4,142,926, 4,258,466, 4,376,947, 4,326,331, 4,313,362, and 4,373,248. Of particular interest to this invention is U.S. Pat. No. 4,750,024, issued June 7, 1988 to John F. Schreck and assigned to Texas Instruments Incorporated, wherein an EPROM is shown to be made by a method similar to that of U.S. Pat. No. 4,258,466, but with an offset floating gate.
EEPROMs, or electrically-erasable, electrically-programmable ROMs, have been manufactured by various processes, usually requiring a much larger cell size than standard EPROMs, and requiring more complex manufacturing processes. EEPROMs can be mounted in opaque plastic packages that reduce the packaging cost. Nevertheless, EEPROMs have been more expensive on a per-bit basis, in comparison with EPROMs, due to larger cell size and to more complex manufacturing processes.
Flash EEPROMs have the advantage of smaller cell size in comparison with standard EEPROMs because the cells are not erased individually. Instead, the array of cells is erased in bulk.
Prior flash-erasable, Fowler-Nordheim tunneling-programmable EEPROMs have usually required two bit lines per cell. Texas Instruments' co-pending application Ser. No. 07/219,529 illustrates an example of an array of such cells. For each column of cells in this array, two parallel bit lines are diffused into the face of the semiconductor layer, one each for the source and drain. Respective metal bit lines overlie and run parallel to the diffused source and drain bit lines. Usually, the pitch of the metal bit lines is a critical limitation in down-scaling the size of the array. As the search continues for devices of smaller and smaller area having the same functionality, it has therefore become desirable to devise an EEPROM cell having less than two bit lines per memory cell.